Frequency dividers may generate lower-frequency signals from higher-frequency signals. Some frequency dividers may generate an output clock having a frequency that is equal to 1/N times the frequency of an input clock, where N is an integer greater than 1. Some frequency dividers may propagate an input signal through a series of flip-flops that are clocked on rising edges of a clock signal, for example, so that each of the flip-flops generates an output signal that is an incrementally delayed version of the input signal. The delayed versions of the input signal may be logically combined to generate an output signal having a frequency equal to 1/N times the frequency of the input signal.
Other frequency dividers may form or operate as an oscillating circuit that generates output signals having a frequency equal to 1/N times the frequency of an input signal. For example, an injection-locked frequency divider may operate as a tuned oscillator that is locked to an input clock frequency divided by N. Injection-locked frequency dividers may be more efficient than flip-flop based frequency dividers at higher frequencies.
When a frequency divided output signal is used for timing one or more components of a circuit or device, it may be desirable to maintain the duty cycle of the frequency divided output signal at a desired and/or constant value.